1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for creating a mask-programmable architecture from standard cells for use in creating systems on a chip.
2. Related Art
The dramatic improvements in semiconductor integration densities in recent years have largely been achieved through corresponding improvements in process technologies involved in manufacturing the semiconductor chips. As semiconductor feature sizes continue to decrease, the cost of producing a set of masks used to manufacture a semiconductor chip has increased considerably. For example, industry analysts predict that the cost of generating a set of masks (˜30 or more masks are typically required) for a single design in a 90 nm process will exceed one million dollars.
Note that mask re-spins are frequently required to correct logic bugs after first silicon, or to deal with changing requirements. Note that requirements frequently change because over the lifetime of a product; various derivatives of a semiconductor chip are required to accommodate changing formats or interfaces.
In order to avoid costly mask re-spins to deal with changing requirements, many designers use field-programmable gate arrays (FPGAs) to implement portions of a design that are likely to change. In this way, it is possible to make changes to a system by simply reprogramming the FPGA without incurring the cost of an additional mask re-spin.
However, there are a number of problems with using FPGAs. Although FPGAs provide a great amount of flexibility, FPGAs are relatively expensive in terms of area, power and delay. For example, implementing a function using an FPGA can consume up to ten times the area and 500 times the power of a standard cell implementation. Furthermore, FPGAs are typically located off-chip, so a considerable delay is typically involved in communicating with the FPGA.
Some developers have also considered integrating FPGA circuitry into conventional semiconductor chips along with other types of circuitry. However, a number of interconnection issues still remain. The interconnect architecture in an FPGA depends on the underlying technology used to achieve programmability. In the case of anti-fuse based technologies, programmability is achieved by selectively blowing the anti-fuses. Hence, such an architecture is field-programmable only once and requires programming hardware. In the case of SRAM-based FPGA technologies, the routing programmability needs access to active silicon, which gives rise to additional complications.
Designers have also considered using a mask-programmable architecture to facilitate re-spins of only a subset of masks to configure the circuitry (see related co-pending non-provisional application by the same inventors as the instant application entitled, “Method and Apparatus for Designing an Integrated Circuit Using a Mask-Programmable Fabric,” having Ser. No. 10/734,399, and filing date 12 Dec. 2003. However, deciding on a basic mask-programmable module to use for a specific family of designs is a tedious process. It requires significant effort from circuit designers and architects to perform various layout, optimization, and characterization operations for the basic mask-programmable module. Generating and characterizing a library using a configurable module requires an effort that is equivalent to that of developing a whole standard cell library.
Hence, what is needed is a method and an apparatus that facilitates developing on a mask-programmable module without the going through the tedious process described above.